Limitations of switch level analysis for bridging faults

Switch level models are widely used for fault analysis of MOS digital circuits. Switch level analysis (SLA) provides significantly more accurate results compared to the gate level models and also avoids the complexities of circuit level analysis. The accuracy of SLA is critically examined, and conditions under which switch level analysis may generate incorrect results are specified. Such conditions may occur when the bulk of a transistor is connected to its source. These conditions are especially applicable under certain types of bridging faults. A simple technique is suggested for accurate switch level modeling under such conditions.